module tb_shiftregC();
    reg load;
    reg in;
    reg sin, clk, reset;
    reg shift;
    wire sout;
    wire q;
    shiftregC dut(shift, load, in, sin, clk, sout,q, reset);
    always
    begin
        clk = 1; #5; clk = 0; #5;
    end
    initial
    begin
        $dumpfile("tb_shiftregC");
        $dumpvars;
        sin=0;load=0;shift=0;in=0;reset=1;#10;reset=0;#5;in=1;
        load=1;#30;
        load=0; shift=1;#100;
        load=1;shift=0;#20;load=0;shift=1;#200;load=1;#200;
        $finish;
    end
endmodule